1. Field of the Invention
The present invention relates to frame alignment loss and recovery at a digital transmission path receive end, including e.g., a demultiplexer, and demultiplexing a digital signal into component signals. More particularly, the invention deals with an alignment loss and recovery device for recognizing a periodic synchronization pattern, such as a frame alignment word, carried by the digital signal, to thereby synchronize a time base delivering various clock signals requried for demultiplexing.
2. Description of the Prior Art
In known alignment loss and recovery devices, a shift register receives the digital signal under the control of a recovered clock signal having a digital signal timing frequency. To extract N-bit words at the recovered clock signal rate, the shift register includes N stages, where N is an integer equal to the number of bits in the alignment word. Each extracted N-bit word is compared in a logic comparator against an alignment word stored in a read only memory such that an alignment word can be detected among the extracted words. By detecting the alignment word, it is possible to synchronize the time base with the digital signal frame frequency and to block and unblock the time base in terms of predetermined numbers of detected alignment words as being correct and incorrect as defined per predetermined error rates.
As matters currently stand, propagation time in programmable memories and other analogous logic circuits is longer than a elementary time slot corresponding to a bit in a digital signal having a high bit rate, on the order of several Mbit/s. It is therefore incompatible to recognize the alignment word among the words extracted from the shift register at the high bit rate digital signal timing frequency using usual memories if a tolerance of a few errors on the detected alignment word is required. Indeed, in a memory used as a logic comparator, each extracted word is compared bit by bit with each bit of erroneous and tolerated alignment words. By way of an example, if the alignment word is made up of N bits, the extracted word is compared with N alignment words having 1 erroneous bit if a maximum tolerance of one error is required. The time to process the extracted word increases as the number of tolerated errors increases. The known devices used for digital signals having a bit rate in the range of a few tens of Mbit/s at the most thus rely on a logic circuit that compares each extracted word only against an alignment word having no errors, and hence tolerate no error bits in the detected alignment word. However, a tolerance margin of at least one error in the alignment word would make it possible to hold frame alignment whenever there is a transient error, as is the case with a micro-break or a one-bit shift in the signal upstream of the demultiplexer.